1. Field of the Invention
This invention relates to semiconductors, and more particularly, to a high-voltage MOS (metal-oxide semiconductor) device and a method for fabricating the same. This MOS device features an increased conductive path for electric current therein and a small area for layout on the chip.
2. Description of Related Art
Conventional MOS devices are generally provided with isolation layers and underlying drift regions so as to separate the source/drain regions from the gates such that the MOS devices can be operable under high-voltage conditions. The semiconductor structure of such a MOS device is described in more detail in the following with reference to FIGS. 1A through 1D.
Referring first to FIG. 1A, a substrate 110 such as a P-type silicon substrate is subjected to thermal oxidation so as to form a pad oxide 111 on the top surface thereof After that, a silicon nitride 112 is formed over the pad oxide 111 by chemical-vapor deposition (CVD). A photolithographic and etching process is then conducted on the wafer for pattern definition and removal of selected portions of the silicon nitride 112 so as to form openings 113 in the silicon nitride 112. The exposed surfaces of the pad oxide 111 are intended for the forming of drift regions in later steps. Subsequently, an ion implantation process is conducted on the wafer so as to implant an N-type dopant such as phosphor ions through the openings 113 into those regions indicated by the reference numeral 14 in the substrate 110 so as to form lightly-doped regions therein.
Referring next to FIG. 1B, in the subsequent step, the wafer is subjected to thermal oxidation such as wet oxidation so as to form isolation layers 115 in the openings 113. The isolation layers 115 can be oxide layers, for example, that are formed by local oxidation of silicon (LOCOS). Through this process, the implanted phosphor ions are also driven in to form N-type lightly-doped drift regions 114.
Referring onward to FIG. 1C, in the subsequent step, an etching process such as wet etching is conducted on the wafer so as to remove the silicon nitride 112 and the pad oxide 111 successively. After that, a gate oxide layer 116 is formed on the substrate 110 either by the CVD method or by thermal oxidation. Subsequently, a conductive layer 117 such as highly-doped polysilicon layer is formed over the gate oxide layer 116 by the CVD method. A photolithographic and etching process is then conducted on the wafer for pattern definition and removal of selected portions of both the conductive layer 117 and gate oxide layer 116 so as to form a gate 118. Next, the gate 118 and the isolation layers 115 are used together as a mask to conduct an ion implantation process on the wafer so as to implant an N-type dopant, such as phosphor ions, into the substrate 110. The doped regions are further heated so as to drive in the implanted ions to form N-type lightly-doped regions 119. Then, the gate 118 and the isolation layers 115 are used together again as a mask to conduct a second ion implantation process on the wafer so as to implant a dopant such as arsenic ions into the substrate 110. The doped regions are further heated so as to drive in the implanted ions to form N.sup.+ heavily-doped source/drain regions 120.
Referring further to FIG. 1D, in the subsequent step, a planarized insulating layer 121 such as borophosphosilicate glass (BPSG) is formed over the wafer. Thereafter, a photolithographic and etching process is conducted on the wafer for removal of selected portions of the planarized insulating layer 121 so as to form the contact holes 122 which penetrate through the planarized insulating layer 121 to expose the source/drain regions 120. Then the contact holes 122 are filled with a metal such as aluminum so as to form contact windows 123.
It is a drawback of the foregoing MOS device that, since the junction between the source/drain regions 120 and the drift regions 114 is small in cross area, the current flowing therethrough is limited to a small magnitude only.
A conventional solution to increase the current is to increase the area of the source/drain regions so as to increase the cross area of the junction. However, this scheme correspondingly increases the layout area of the source/drain regions on the wafer and thus is contradictory to the layout rules of the MOS device.